1) Field of the Invention
This invention relates generally to fabrication and structures of semiconductor devices and more particularly to the fabrication of an Electro Static Discharge (ESD) device and more particularly an Electro Static Discharge (ESD) device using a silicide process. The invention related to a device for on-chip ESD protection.
2) Description of the Prior Art
The n-type MOS transistor has been widely employed as the primary component for an ESD protection circuit in semiconductor IC devices. It is well known that silicidation of the drain and LDD junctions reduce ESD performance significantly. Most salicided process have a removal option which allows unsalicided areas (e.g., resistors) to be formed and use ESD implant to make junction deeper and to overdose the lightly doped region of the LDD for better ESD performance.
NMOS transistors stacked in a cascade configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. However, this kind of device has high snapback voltage. Also, the high snapback voltage of the stacked NMOS degrades its IT2 (IT2 is the second breakdown trigger current)) since the power dissipation is great. The IT2 is the current at or before the MOS gets into secondary breakdown (thermal/permanent damages) The higher the It2, the more robust the NMOS and the higher the ESD threshold. For the process technology where the silicide block and abrupt junction steps were are not available, a biasing network was necessary to ensure uniform triggering of all fingers. So, the need for high voltage tolerant I/O's severely complicates ESD protection.
FIG. 5A shows a single poly N-MOS device that is used in the prior art as an ESD device. The structure and snap back mechanism are described below. The single-poly N-MOS device is shown in cross section and layout in FIG. 5A. FIG. 5B shows a top plan view. FIG. 5C shows the IV curve and snap back curve for the ESD device. Vsp is the snapback holding voltage. FIG. 5D shows the electrical schematic of the device in FIG. 5A. When a short-duration (100 to 110 ns) constant current pulse is applied to the drain with the source and gate tied to the substrate (substrate grounded), the device should have the I-V characteristic shown in FIG. 5C. At normal operation, the device is off because the gate is grounded. When the drain breakdown voltage, BVdss is reached, current starts to flow as a result of impact ionization of die reverse-biased drain junction. At current It1, and voltage Vt1, the device triggers into snapback. The trigger current It1 and voltage is related to the channel length and BVdss. Note that the trigger voltage point (Vt1, It1,) is not the same as BVdss. BVdss, usually is defined as the drain junction avalanche breakdown voltage at a specified drain current density. The trigger point is the point that has the highest voltage just before snapback. The snapback region of the I-V curve is roughly linear and, therefore, may be represented by a snapback voltage Vsb and a differential resistance Rsb. The snapback voltage Vsb is defined as the linear extrapolation of the snapback region back to zero current. Care must be taken to avoid defining Vb and Rb by extrapolating from low current values near the point where the I-V curve changes slope from negative to positive. Therefore, the values of Vsb and Rsb were obtained from measurements made at high currents with the transmission-line pulse technique. Because the high-current values are relevant to ESD events, we need to use them rather than the low-current values when designing for protection against ESD. With sufficiently high current It2, flowing in the snapback region, the device triggers into second breakdown. We define a second trigger point (Vt2, It2) corresponding to the triggering from snapback into second breakdown. Second breakdown is the term used for power bipolar devices to indicate the regime of thermal runaway and current-instability.
The following patents show related ESD devices: U.S. Pat. No. 5,898,205(Lee), U.S. Pat. No. 5,519,242(Avery), U.S. Pat. No. 5,969,923(Avery), U.S. Pat. No. 5,559,352(Hsue et al.), U.S. Pat. No. 5,043,782(Avery) and U.S. Pat. No. 5,689,113(Li et al.).
There is a challenge to device a new ESD device for silicide process that improve the ESD performance by lowering the Vt1 and lower leakage.